In a distributed virtual memory (DVM) system, such as used in Advanced RISC Machines (ARM) processors, DVM messages from a DVM source (e.g., a central processor unit (CPU)) are broadcast to all other DVM sources and to all DVM destinations (e.g., a system memory management unit (SMMU)). The DVM messages are distributed by a coherent interconnect and/or a DVM network, and such components gather responses from the DVM sources and destinations, merge the responses into a single response, and return a single response to the sending DVM source. Thus, the total response time for a DVM message is controlled by the slowest response.